1. Field of the Invention
The present invention generally relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device that includes buried wirings formed by using Chemical Mechanical Polishing technique.
This application is a counterpart of Japanese patent application, Serial Number 126615/2002, filed Apr. 26, 2002, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
A method of manufacturing buried wirings by using a CMP (it is herein after referred to as CMP) method in a semiconductor device manufacturing process has been developed in recent years. According to this method, trench patterns for wirings, which are formed in an insulating film, are first formed, and a conductive layer is deposited thereon, whereby a conductor is embedded in each of the trench patterns. In order to remove the unnecessary conductor other than the conductor embedded in the trench patterns, the conductive layer is thereafter polished by the CMP method until the upper surface of the insulating film is exposed. The conductive layer left only in each of the trench patterns by this polishing is used as a wiring. In the present method, copper pattern processing becomes easy in particular.
However, the aforementioned CMP method will cause a phenomenon that the polishing of the conductive layer in each trench pattern proceeds much more than the polishing on the insulating film. As a result, depressions are formed on a wiring upper surface after the formation of each buried wiring. This is called a xe2x80x9cdishing phenomenonxe2x80x9d. The depth of each depression produced due to this dishing phenomenon increases depending on an open width of each of the trench patterns. When the open width of the trench pattern is 10 xcexcm or more, for example, the depth reaches 150 nm or more. Therefore, the surface to be polished, of a wiring having a broad open width in particular cannot be planarized.
When an interlayer insulating film is formed on the polished surface in which such a dishing phenomenon as described above has occurred, depressions corresponding to the depressions on the polished surface appear on the surface of the interlayer insulating film. Let""s assume that an upper layer buried wiring is formed on the interlayer insulating film having the depressions formed in such a surface, by using the CMP method according to a procedure similar to the above. In doing so, the conductive layer remains even within the depressions in addition to within the trench patterns formed in the interlayer insulating film as intended for the wiring. When such a conductive layer is located between the conductive layers used as the original wirings, the wirings not to be originally connected are connected to each other therebetween, thereby causing a short. Thus, when a semiconductor device having a multilayered wiring structure is fabricated, the occurrence of the dishing phenomenon contributes to a reduction in yield.
Therefore, various methods have been proposed to prevent the dishing phenomenon. There is known, for example, a method of providing posts in a wiring trench at narrow intervals of 1 xcexcm or less where wirings each having a broad open width of 10 xcexcm or more, for example (see Japanese Laid-Open Patent No. 9-8039). There is also known a method of defining slits each having a narrow interval within a wiring trench as a method similar to above (see Japanese Laid-Open Patent No. 10-229085). These methods aim to divide the interior of a broad wiring trench into areas each having a narrow width to thereby prevent the dishing phenomenon.
There are also known one wherein a slit trench pattern having a predetermined width is provided in a central portion of a wide wiring trench to increase the thickness of a copper-plated film in a central area of the wide wiring trench, thereby preventing a dishing phenomenon (see Japanese Laid-Open Patent No. 2001-217248), and one provided with a plurality of protrusions which extend out up to some midpoint of a step of an interlayer insulating film (see Japanese Laid-Open Patent No. 2001-156071).
One of these manufacturing methods will be described by using the drawings.
As shown in FIG. 2(A), an insulating film 22 having a predetermined thickness is formed on a semiconductor substrate 21. Afterwards, a wiring 23 is formed on the surface of the insulating film 22 and the insulating film 22 is further deposited to planarize the surface thereof.
Next, opening 24 as a via hole, which extends through to the wiring 23, is defined in the insulating film 22 by anisotropic dry etching with an unillustrated resist as a mask. Simultaneously with it, trench patterns 25 are formed in a central area of a wide wiring trench of the insulating film 22.
Next, as shown in FIG. 2(B), a non-photosensitive organic coating film (antireflection film) 26 is applied onto a surface including the interiors of the opening 24 and the trench patterns 25. Next, a photoresist 27 is patterned thereon. Next, the organic coating film 26 is removed by etching with the photoresist 27 as a mask. Further, an upper layer portion of the insulating film 22 and the organic coating film 26 located at the same height as the upper layer portion are etched using an etching gas of a different kind with the same photoresist 27 as the mask. Afterwards, the photoresist 27, the organic coating film 26 placed under the photoresist 27, and the organic coating film 26 left inside the opening 24 and the trench patterns 25 are removed.
In doing so, narrow wiring trenches 28 and a wide wiring trench 29 are defined in the insulating film 22 together with the opening 24 as shown in FIG. 2(C). The trench patterns 25 obtained by polishing only the heights of the narrow wiring trenches 28 are formed in a central area of the wide wiring trench 29. Afterwards, wirings are formed on surfaces thereof by the CMP method (see Japanese Laid-Open Patent No. 2001-217248).
However, the first two conventional examples are respectively accompanied by a drawback that although the manufacture thereof is relatively easy, the sectional area of the portion used for the conductor for each wiring becomes small due to the insulating posts and the slits and hence wiring resistance increases.
Also the final two conventional examples are respectively accompanied by a drawback that while no insulator exists in the upper layer portion of each wiring and wiring resistance with respect to a current flowing therethrough does not increase, they become rather difficult in manufacture. Namely, there is a need to accurately control the pressure and flow rate of a gas at the etching of the organic coating film and the insulating film, and the time required to execute the etching in order to suitably adjust the heights of the trench patterns. When an adjustment to the depth of each trench pattern goes wrong and the trench pattern is made deep excessively, parasitic capacitance between the wiring located below the trench pattern and the broad wiring will increase where the wiring is located therebelow.
According to one aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method includes forming a first insulating layer over a semiconductor substrate; forming an etching resistant film on a first area of the first insulating layer; forming a second insulating layer over the first insulating layer including the etching resistant film; defining a plurality of trenches exposing a surface of the etching resistant film in the second insulating layer; removing a part of surface of the second insulating layer, which is located at an upper portion of the etching resistant film; forming a conductive layer on the second insulating layer including the plurality of trenches; and polishing the conductive layer until the surface of the second insulating layer is exposed.
The above and further objects and novel features of the invention will more fully appear from the following detailed description, appended claims and the accompanying drawings.